A DMOS (Double Diffused MOSFET) structure is adopted as a structure of a power MOSFET that is used as a power semiconductor device. In the DMOS structure, a semiconductor substrate having an n-type layer (an epitaxial layer) formed on an n+-type substrate configured to function as a drain is used. A p-type layer to be a body region is locally formed on a surface of the n-type layer by an ion implantation and the like. Also, an n+-type layer to be a source region is locally formed in the p-type layer on the surface. A switching (on-and-off) of a channel in the body region just below a gate electrode adjacent to the n+-type layer to be a source region is controlled by a voltage applied to the gate electrode, so that a switching operation is performed. The MOSFET having the above configuration is disclosed in WO 2009/128382. The semiconductor substrate is made of Si or silicon carbide (SiC). In any case, it is possible to obtain a power semiconductor device having the same structure although the manufacturing processes thereof are different.
Without being limited to the technology disclosed in WO 2009/128382, in the above DMOS structure, a source electrode is formed on the surface, and the source electrode is connected with the source region (n+-type layer) of the surface and the body region (p-type layer). Since a large current flows through the source electrode during an operation, it is necessary to reduce a contact resistance between the source electrode and the n+-type layer, p-type layer. According to the technology disclosed in WO 2009/128382, a material of an electrode directly contacting the same is optimized to reduce the contact resistance.